1. Field of the Invention
The present invention relates to a method for preparing a thin-film transistor which is used mainly in a liquid crystal display of an active matrix driving system, an image sensor, a thermal head and the like, and relates to a thin-film transistor obtained by this preparing method. The present invention can be also applicable to MOS transistor to be used for LSI.
2. Description of the Related Art
Up to this time, a thin film transistor (hereinafter referred to as TFT) has been used for a liquid crystal display of a small television set and a computer system, an image sensor used for a facsimile machine, and a thermal head. At present, an amorphous silicon TFT is being most popularly developed, on account of its feature that it can be prepared by a comparatively easy method and it is easy to be formed on a large area substrate. The amorphous silicon TFT, however, has a drawback that the mobility of its electron and hole is very small such as in the order of 1 cm2/V·S and0.1 cm2/V·S respectively. This drawback causes an insufficient performance especially in switching speed in order to construct a driving circuit on the same substrate, though it does not pose a big problem in switching of e.g., each one pixel of a liquid crystal display or each bit of an image sensor.
On the other hand, a polycrystal silicon TFT being used in a small type liquid crystal television or an image sensor, has about 10 cm2/V·S or more of both mobilities of electron and hole, and the product actually constructed with the driving circuit has been on sale. This polycrystal silicon TFT usually has a coplanar type structure, namely; the structure that each electrode of gate, source, and drain is all positioned opposite the substrate toward a silicon channel part.
In case of such TFT as the above structure, an impurity introduction into a semiconductor film of source and drain part will be usually carried out by such method as ion implantation, ion doping, and plasma doping, using a self-alignment with the mask of gate electrode. Further, an activation of impurity will be effected by heat-annealing or laser-annealing at the temperature of 600° C. or more, and after that, TFT will be finally prepared by forming an interlayer insulating film and a metal wiring and so on.
Such prepared coplanar type TFT has a structure in which an impurity region is provided in a positioning relation as shown in FIG. 2(a). In this structure, high-density doping layers 20 and 21 are provided just beside a gate electrode 22/a gate insulating film layer 23, or one part thereof is provided overlapping with the gate electrode. For that reason, when such TFT is operated, an electric field is concentrated in the vicinity of the drain 20 to generate so-called hot carriers. This causes degradation of linearity of mutual conductance (Gm) and inconvenience that the reliability is lowered by degradation of a device characteristic such as degradation of mutual conductance (Gm) in a long period use. Furthermore, there occurs a degradation that an electric current will be easily leaked through a center area level of band gaps existing in the neighborhood of the drain 20.
As a solving means for the above-mentioned inconveniences, LDD (Light doped drain) structure has been adopted in LSI, and also it has been investigated in TFT recently and adopted partly. A preparing method for TFT of such structure takes the following steps;
(1) Firstly, a gate silicon oxide film 23 and a silicon film 22 doped with an impurity in a high concentration will be formed on a silicon which is patterned in an island state. Then, a gate electrode and a gate silicon oxide film will be formed by patterning these films. After an impurity is introduced into an island state silicon part (source 21, drain 20), where is not covered with the gate electrode 22, in a low concentration of 1017 to 1019 atoms/cm3, a silicon oxide film 24 will be formed using a film-forming method with a good step-coverage, thereby obtaining the state of FIG. 2(b). At this time, in the side wall of the gate part, silicon oxide film will be accumulated thickly.
(2) Then, by etching this silicon oxide film 24 using such high anisotropic etching method as RIE (Reactive Ion Etching), the silicon oxide film 25 will be remained in the neighborhood of side area of the gate electrode 22. In this way, the state of FIG. 2(c) will be obtained. The thick film part on side area of this gate electrode will be used as a spacer for the later doping.
(3) Next, using the above prepared silicon oxide film 25 (Spacer for doping) neighboring the gate electrode 22 as a mask, an ion implantation of impurity will be executed in a high, concentration (1020 to 1021 atoms/cm3). After that, source 28 and drain 27 will be completed by activating the impurity, and also LDD part 28 where the impurity is introduced in a low concentration will be completed, under the silicon oxide film 25 nearby the gate electrode 22, thus obtaining the state of FIG. 2(d). In this way LDD structure can be formed. The above (1) to (3) processes, however, will be added in comparison with the case of preparation for the conventional transistor as shown in FIG. 2(a), the result being that it is disadvantageous in the point of yielding and cost.